1. Field of the Invention
The present invention relates to a microprocessor capable of executing instructions, each instruction including a plurality of sub-instructions, in an instruction group.
2. Description of the Related Art
Microprocessors having the function of parallel processing such as pipeline are widely and commonly used in order to increase the performance of the microprocessor such as operation speed and so on. A VLIW (Very Long Instruction Word) architecture has been proposed and used in microprocessors as one of methods for parallel processing.
In order to increase the performance such as the operation speed and so on, the microprocessors of the VLIW architecture can execute a plurality of sub instructions included in a single instruction, in parallel, that are used for controlling the operation of a plurality of operation units incorporated in the microprocessor. Each of the plurality of operation units can operate independently to each other.
Because the conventional microprocessor of the VLIW architecture has the configuration described above, in the case that sub-instructions can not be executed in parallel when a data hazard happens between operation units, a NOP (No Operation) instruction is provided to the operation unit that can not execute the sub instruction, namely the operation unit must wait to initiate the execution of the sub instruction until the data hazard is completely eliminated.
This drawback of the conventional microprocessor of the VLIW architecture causes to decrease the efficiency of decoding and executing the instructions.
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a microprocessor of a VLIW architecture capable of executing instructions, each comprising a plurality of sub-instructions, and having a function to increase the operation efficiency by controlling the operation flow in which a following sub instruction is executed by the operation unit that has executed a preceding sub instruction when another operation unit can not execute the following sub instruction by the occurrence of a data hazard in a sequential processing per operation unit, for example.
In accordance with a preferred embodiment of the present invention, a microprocessor comprises memory circuit, instruction decode unit, a plurality of registers, a plurality of instruction execution means, and control circuit. The memory circuit stores instructions for a single operation. Each instruction includes a plurality of sub instructions for controlling a plurality of operations and data. The instruction decode unit decodes the instructions that are read from said memory circuit. The plurality of registers stores control data to control the execution of said instructions. The plurality of instruction execution means, that are connected to said instruction decode unit, execute said plurality of sub instructions sequentially and independently in parallel, based on decoded results of said instructions transferred from said instruction decode unit and control data stored in said plurality of registers. The control circuit, that is incorporated in said instruction decode unit, controls said plurality of instruction execution means so that a first instruction execution means that has executed a first sub instruction can execute a following second sub instruction when said plurality of instruction execution means execute said plurality of sub instructions sequentially.
In the microprocessor as another preferred embodiment according to the present invention, said control circuit controls so that said first instruction execution means executes said following second sub instruction when said control circuit decides that a second instruction execution means in said plurality of instruction execution means can not execute said following second sub instruction.
In the microprocessor as another preferred embodiment according to the present invention, said control circuit controls so that second instruction execution means in said plurality of instruction execution means executes said following second sub instruction when said control circuit decides that said second instruction execution means can not execute said following second sub instruction.
In the microprocessor as another preferred embodiment according to the present invention, said control circuit comprises decision circuit, an exchange circuit, first selector, and a plurality of selectors. The decision circuit inputs said instructions, each of said instructions includes said plurality of sub instructions, transferred from said memory circuit and analyzes said instructions, and decides that one of said plurality of instruction execution means can execute one of said plurality of sub instructions. The exchange circuit exchanges bit strings designating said plurality of sub instructions under controlling of said decision circuit. The first selector selects one of said plurality of sub instructions under the control of said decision circuit, and outputs said selected sub instruction. Each of the plurality of selectors is connected to said first selector and each of said plurality of instruction execution means, and each selects one of said selected sub instruction and NOP instruction under controlling of said decision circuit.